Browsing by author "Tirrito, Matteo"
Now showing items 1-6 of 6
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Characterization of highly doped Si:P, Si:As and Si:P:As epi layers for source/drain epitaxy
Rosseel, Erik; Tirrito, Matteo; Porret, Clément; Douhard, Bastien; Meersschaut, Johan; Hikavyy, Andriy; Loo, Roger; Horiguchi, Naoto; Pourtois, Geoffrey; Nakazaki, Nobuya; Tolle, John (2019) -
Characterization of highly doped Si:P, Si:As and Si:P:As Epi layers for source/drain epitaxy
Rosseel, Erik; Tirrito, Matteo; Porret, Clément; Douhard, Bastien; Meersschaut, Johan; Hikavyy, Andriy; Loo, Roger; Horiguchi, Naoto; Pourtois, Geoffrey; Nakazaki, Nobuya; Tolle, John (2019-06) -
Contact resistivity of highly doped Si:P, Si:As and Si:P:As Epi layers for source/drain epitaxy
Rosseel, Erik; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Tirrito, Matteo; Douhard, Bastien; Richard, Olivier; Horiguchi, Naoto; Khazaka, Rami (2020-09) -
Contact resistivity of highly doped Si:P, Si:As and Si:P:As Epi layers for source/drain epitaxy
Rosseel, Erik; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Tirrito, Matteo; Douhard, Bastien; Richard, Olivier; Horiguchi, Naoto; Khazaka, Rami (2020-07) -
Source/drain materials for Ge nMOS devices: phosphorus activation in epitaxial Si, Ge, Ge1xSnx and SiyGe1xySnx
Vohra, Anurag; Makkonen, Ilja; Pourtois, Geoffrey; Slotte, Jonatan; Porret, Clément; Rosseel, Erik; Khanam, Afrina; Tirrito, Matteo; Douhard, Bastien; Loo, Roger; Vandervorst, Wilfried (2020-05) -
Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration
Porret, Clément; Vohra, Anurag; Hikavyy, Andriy; Rosseel, Erik; Huang, Yan-Hua; Tirrito, Matteo; Kohen, David; Margetis, Joe; Tolle, John; Petersen Barbosa Lima, Lucas; Khazaka, Rami; Langer, Robert; Loo, Roger (2019)