Browsing by author "Schuddinck, Pieter"
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5nm: has the time for a device change come?
Raghavan, Praveen; Garcia Bardon, Marie; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Baert, Rogier; Debacker, Peter; Verkest, Diederik; Thean, Aaron (2016) -
A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
Gupta, Mohit; Weckx, Pieter; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Cosemans, Stefan; Ryckaert, Julien; Dehaene, Wim (2021) -
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Sherazi, Yasser; Chava, Bharani; Debacker, Peter; Garcia Bardon, Marie; Schuddinck, Pieter; Firouzi, Farshad; Raghavan, Praveen; Mercha, Abdelkarim; Verkest, Diederik; Ryckaert, Julien (2016) -
Buried Bitline for sub-5nm SRAM Design
Mathur, R.; Bhargava, M.; Annamalai, S.; Chong, Y. K.; Sinha, S.; Cline, B.; Kulkarni, J. P.; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Ryckaert, Julien; Gupta, Anshul (2020) -
Buried Interconnects for Sub-5 nm SRAM Design
Mathur, R.; Bhargava, M.; Cline, B.; Salahuddin, Shairfe Muhammad; Gupta, Anshul; Schuddinck, Pieter; Ryckaert, Julien; Kulkarni, J.P. (2022) -
CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
Liu, Hsiao-Hsuan; Salahuddin, Shairfe Muhammad; Chan, Boon Teik; Schuddinck, Pieter; Xiang, Yang; Hellings, Geert; Weckx, Pieter; Ryckaert, Julien; Catthoor, Francky (2023) -
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
Liu, Hsiao-Hsuan; Schuddinck, Pieter; Pei, Zhenlin; Verschueren, Lynn; Mertens, Hans; Salahuddin, Shairfe Muhammad; Hiblot, Gaspard; Xiang, Yang; Chan, Boon Teik; Subramanian, Sujith; Weckx, Pieter; Hellings, Geert; Garcia Bardon, Marie; Ryckaert, Julien; Pan, Chenyun; Catthoor, Francky (2023) -
Circuit and product level assessment of emerging fully depleted channel devices: FinFET and UTBOX-SOI
Badaroglu, Mustafa; Dehan, Morin; Garcia Bardon, Marie; Miranda Corbalan, Miguel; Zuber, Paul; Schuddinck, Pieter; Mallik, Arindam; Mercha, Abdelkarim; Verkest, Diederik (2012) -
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Design enablement of CFET devices for sub-2nm CMOS nodes
Zografos, Odysseas; Chehab, Bilal; Schuddinck, Pieter; Mirabelli, Gioele; Kakarla, Naveen; Xiang, Yang; Weckx, Pieter; Ryckaert, Julien (2022-05-19) -
Design technology co-optimization for N10
Ryckaert, Julien; Raghavan, Praveen; Baert, Rogier; Garcia Bardon, Marie; Dusa, Mircea; Mallik, Arindam; Sakhare, Sushil; Vandewalle, Boris; Wambacq, Piet; Chava, Bharani; Croes, Kris; Dehan, Morin; Jang, Doyoung; Leray, Philippe; Liu, Tsung-Te; Miyaguchi, Kenichi; Parvais, Bertrand; Schuddinck, Pieter; Weemaes, Philippe; Mercha, Abdelkarim; Boemmels, Juergen; Horiguchi, Naoto; McIntyre, Greg; Thean, Aaron; Tokei, Zsolt; Cheng, Shaunee; Verkest, Diederik; Steegen, An (2014) -
Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm
Chehab, Bilal; Ryckaert, Julien; Schuddinck, Pieter; Weckx, Pieter; Horiguchi, Naoto; Mirabelli, Gioele; Spessot, Alessio; Na, Myung Hee (2021) -
Device challenges for logic scaling for sub-5 nm node
Jang, Doyoung; Garcia Bardon, Marie; Yakimets, Dmitry; Schuddinck, Pieter; Ragnarsson, Lars-Ake; Sharan, Neha; Parvais, Bertrand; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2018) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Device exploration of nanosheet transistors for sub-7nm technology node
Jang, Doyoung; Yakimets, Dmitry; Eneman, Geert; Schuddinck, Pieter; Garcia Bardon, Marie; Raghavan, Praveen; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
Digital circuit design and benchmarking for FDSOI devices: FinFET and UTBOX
Badaroglu, Mustafa; Zuber, Paul; Garcia Bardon, Marie; Miranda Corbalan, Miguel; Schuddinck, Pieter; Mercha, Abdelkarim (2012) -
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Jang, Doyoung; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron (2015) -
Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
DTCO flow for device exploration
Yakimets, Dmitry; Schuddinck, Pieter; Matagne, Philippe; Parvais, Bertrand; Mocuta, Anda (2018)