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Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
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Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
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Date
2015
Proceedings Paper
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31617.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Huynh Bao, Trong
;
Sakhare, Sushil
;
Ryckaert, Julien
;
Yakimets, Dmitry
;
Mercha, Abdelkarim
;
Verkest, Diederik
;
Thean, Aaron
;
Wambacq, Piet
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Abstract
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1921
since deposited on 2021-10-22
Acq. date: 2026-01-07
Citations
Metrics
Views
1921
since deposited on 2021-10-22
Acq. date: 2026-01-07
Citations