Publication:

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

Date

2022
Journal article
https://doi.org/10.1109/TED.2022.3205561
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dc.contributor.authorVeloso, Anabela
dc.contributor.authorJourdain, Anne
dc.contributor.authorRadisic, Dunja
dc.contributor.authorChen, Rongmei
dc.contributor.authorArutchelvan, Goutham
dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorStucchi, Michele
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorHosseini, Maryam
dc.contributor.authorHopf, Toby
dc.contributor.authorD'have, Koen
dc.contributor.authorWang, Shouhua
dc.contributor.authorDupuy, Emmanuel
dc.contributor.authorMannaert, Geert
dc.contributor.authorVandersmissen, Kevin
dc.contributor.authorIacovo, Serena
dc.contributor.authorMarien, Philippe
dc.contributor.authorChoudhury, Subhobroto
dc.contributor.authorSchleicher, Filip
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorJourdain, Anne
dc.contributor.imecauthorRadisic, Dunja
dc.contributor.imecauthorChen, Rongmei
dc.contributor.imecauthorArutchelvan, Goutham
dc.contributor.imecauthorO'Sullivan, Barry
dc.contributor.imecauthorArimura, Hiroaki
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dc.date.accessioned2022-12-09T10:37:33Z
dc.date.available2022-10-15T02:51:00Z
dc.date.available2022-12-09T10:37:33Z
dc.date.issued2022
dc.identifier.doi10.1109/TED.2022.3205561
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40572
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage7173
dc.source.endpage7179
dc.source.issue12
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages7
dc.source.volume69
dc.title

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

dc.typeJournal article
dspace.entity.typePublication
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