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Packaging approach for nano-CMOS wiring

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dc.contributor.authorBalachandran, Jayaprakash
dc.contributor.authorBrebels, Steven
dc.contributor.authorCarchon, Geert
dc.contributor.authorDe Raedt, Walter
dc.contributor.authorNauwelaers, Bart
dc.contributor.authorBeyne, Eric
dc.contributor.imecauthorBrebels, Steven
dc.contributor.imecauthorDe Raedt, Walter
dc.contributor.imecauthorNauwelaers, Bart
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBrebels, Steven::0000-0002-1568-0286
dc.contributor.orcidimecDe Raedt, Walter::0000-0002-7117-7976
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2021-10-16T00:43:50Z
dc.date.available2021-10-16T00:43:50Z
dc.date.issued2005-06
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10054
dc.source.beginpage156
dc.source.conferenceProceedings of the 15th European Microelectronics and Packaging Conference - EMPC
dc.source.conferencedate12/06/2005
dc.source.conferencelocationBrugge Belgium
dc.source.endpage161
dc.title

Packaging approach for nano-CMOS wiring

dc.typeProceedings paper
dspace.entity.typePublication
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