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Integration of GAA Monolayer MoS2 Nanosheet FETs with Gate First Process for Future 2D CFET Scaling

 
dc.contributor.authorXi, Fengben
dc.contributor.authorSharma, Himanshu
dc.contributor.authorWu, Xiangyu
dc.contributor.authorSchram, Tom
dc.contributor.authorConlon, Daire
dc.contributor.authorGrubbs, Robert K.
dc.contributor.authorKumar, Pawan
dc.contributor.authorNgo, Tien Dat
dc.contributor.authorGhosh, Souvik
dc.contributor.authorHan, Fei
dc.contributor.authorvan Dorp, Dennis
dc.contributor.authorVerreck, Devin
dc.contributor.authorSutar, Surajit
dc.contributor.authorSmets, Quentin
dc.contributor.authorLin, Dennis
dc.contributor.authorBanerjee, Kaustuv
dc.contributor.authorLockhart de la Rosa, Cesar Javier
dc.contributor.authorGoux, Ludovic
dc.contributor.authorKar, Gouri Sankar
dc.contributor.imecauthorXi, Fengben
dc.contributor.imecauthorSharma, Himanshu
dc.contributor.imecauthorWu, Xiangyu
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorConlon, Daire
dc.contributor.imecauthorGrubbs, Robert K.
dc.contributor.imecauthorKumar, Pawan
dc.contributor.imecauthorNgo, Tien Dat
dc.contributor.imecauthorGhosh, Souvik
dc.contributor.imecauthorHan, Fei
dc.contributor.imecauthorvan Dorp, Dennis
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorSutar, Surajit
dc.contributor.imecauthorSmets, Quentin
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorBanerjee, Kaustuv
dc.contributor.imecauthorGoux, Ludovic
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorLockhart de la Rosa, Cesar Javier
dc.contributor.orcidimecXi, Fengben::0000-0002-1616-1525
dc.contributor.orcidimecSharma, Himanshu::0000-0002-1938-2489
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecKumar, Pawan::0000-0002-5764-2915
dc.contributor.orcidimecNgo, Tien Dat::0009-0009-7185-308X
dc.contributor.orcidimecGhosh, Souvik::0000-0002-9647-7967
dc.contributor.orcidimecHan, Fei::0009-0004-2081-2521
dc.contributor.orcidimecvan Dorp, Dennis::0000-0002-1085-4232
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecSutar, Surajit::0000-0003-3114-718X
dc.contributor.orcidimecSmets, Quentin::0000-0002-2356-5915
dc.contributor.orcidimecLin, Dennis::0000-0002-1577-6050
dc.contributor.orcidimecBanerjee, Kaustuv::0000-0001-8003-6211
dc.contributor.orcidimecGoux, Ludovic::0000-0002-1276-2278
dc.contributor.orcidimecWu, Xiangyu::0000-0002-6607-1819
dc.contributor.orcidimecLockhart de la Rosa, Cesar Javier::0000-0002-1401-0141
dc.date.accessioned2025-04-14T13:29:18Z
dc.date.available2025-02-02T17:54:59Z
dc.date.available2025-04-14T13:29:18Z
dc.date.issued2024
dc.description.wosFundingTextThe authors gratefully acknowledge the contributions of the imec pilot-line, imec Xplore Lab process support and AMSIMEC characterization teams. The authors also thank COVENTOR from Lam research for the access to the SEMulator3D software, and the technical support. The authors would also like to thank the entire IMEC 2D project team for the discussions, in particular, Bavo Storms, Rudy Verheyen, Jean-Francois de Marneffe, Han Han, and Lixiang Wu for their assistance. This research was funded by the imec IIAP core CMOS programs and from the European Union's Graphene Flagship grant agreement No. 952792.
dc.identifier.doi10.1109/ESSERC62670.2024.10719449
dc.identifier.eisbn979-8-3503-8813-8
dc.identifier.isbn979-8-3503-8814-5
dc.identifier.issn1930-8833
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45157
dc.publisherIEEE
dc.source.beginpage121
dc.source.conference50th IEEE European Solid-State Electronics Research Conference (ESSERC)
dc.source.conferencedateSEP 09-12, 2024
dc.source.conferencelocationBruges
dc.source.endpage124
dc.source.journalN/A
dc.source.numberofpages4
dc.title

Integration of GAA Monolayer MoS2 Nanosheet FETs with Gate First Process for Future 2D CFET Scaling

dc.typeProceedings paper
dspace.entity.typePublication
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