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Multi-Vt Gate Stack Technologies for Nanosheet and CFET Devices

 
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dc.contributor.authorArimura, Hiroaki
dc.contributor.authorFranco, Jacopo
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorVandooren, Anne
dc.contributor.authorBrus, Stephan
dc.contributor.authorMaqsood, W.
dc.contributor.authorConard, Thierry
dc.contributor.authorVerni, G. Alessio
dc.contributor.authorMaes, J. W.
dc.contributor.authorKannan, B.
dc.contributor.authorGivens, M.
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorArimura, H.
dc.contributor.imecauthorFranco, J.
dc.contributor.imecauthorRagnarsson, L-A
dc.contributor.imecauthorVandooren, A.
dc.contributor.imecauthorBrus, S.
dc.contributor.imecauthorMaqsood, W.
dc.contributor.imecauthorConard, T.
dc.contributor.imecauthorHoriguchi, N.
dc.date.accessioned2024-10-27T16:52:59Z
dc.date.available2024-10-27T16:52:59Z
dc.date.issued2024
dc.identifier.doi10.1109/SNW63608.2024.10639201
dc.identifier.eisbn979-8-3503-9163-3
dc.identifier.isbn979-8-3503-9164-0
dc.identifier.issn2161-4636
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44692
dc.publisherIEEE
dc.source.beginpage47
dc.source.conferenceIEEE Silicon Nanoelectronics Workshop (SNW) / Symposium on VLSI Technology and Circuits
dc.source.conferencedate2024-06-15
dc.source.conferencelocationHonolulu
dc.source.endpage48
dc.source.numberofpages2
dc.title

Multi-Vt Gate Stack Technologies for Nanosheet and CFET Devices

dc.typeProceedings paper
dspace.entity.typePublication
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