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Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
Publication:
Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
Date
2017
Proceedings Paper
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36672.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Vaisman Chasin, Adrian
;
Bury, Erik
;
Kaczer, Ben
;
Franco, Jacopo
;
Roussel, Philippe
;
Ritzenthaler, Romain
;
Mertens, Hans
;
Horiguchi, Naoto
;
Linten, Dimitri
;
Mocuta, Anda
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1951
since deposited on 2021-10-24
Acq. date: 2025-10-23
Citations
Metrics
Views
1951
since deposited on 2021-10-24
Acq. date: 2025-10-23
Citations