Publication:

Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects

Date

2017
Proceedings Paper
Simple item page Full metadata Statistics
 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0001-5490-0416
cris.virtual.orcid0000-0002-5847-3949
cris.virtual.orcid0000-0002-9940-0260
cris.virtual.orcid0000-0001-8434-1838
cris.virtual.orcid0000-0002-0402-8225
cris.virtual.orcid0000-0002-1484-4007
cris.virtual.orcid0000-0002-7382-8605
cris.virtual.orcid0000-0002-8615-3272
cris.virtualsource.department9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.department037e6881-9aff-485e-9d58-d5383949642f
cris.virtualsource.department8fc98104-5797-4ad7-ab96-253e6c50458d
cris.virtualsource.department63eea5a8-b81a-4bb2-aa67-715ba610971a
cris.virtualsource.departmentf2e648b4-91e6-42de-bb5d-66326414095e
cris.virtualsource.department812f2909-a81b-4593-9b32-75331cffa35c
cris.virtualsource.department54f24b6a-b745-4c59-a5bc-058756e94864
cris.virtualsource.department112e9a94-6aa4-4c28-96ec-777b0ea053f5
cris.virtualsource.orcid9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.orcid037e6881-9aff-485e-9d58-d5383949642f
cris.virtualsource.orcid8fc98104-5797-4ad7-ab96-253e6c50458d
cris.virtualsource.orcid63eea5a8-b81a-4bb2-aa67-715ba610971a
cris.virtualsource.orcidf2e648b4-91e6-42de-bb5d-66326414095e
cris.virtualsource.orcid812f2909-a81b-4593-9b32-75331cffa35c
cris.virtualsource.orcid54f24b6a-b745-4c59-a5bc-058756e94864
cris.virtualsource.orcid112e9a94-6aa4-4c28-96ec-777b0ea053f5
dc.contributor.authorVaisman Chasin, Adrian
dc.contributor.authorBury, Erik
dc.contributor.authorKaczer, Ben
dc.contributor.authorFranco, Jacopo
dc.contributor.authorRoussel, Philippe
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorMertens, Hans
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorLinten, Dimitri
dc.contributor.authorMocuta, Anda
dc.contributor.imecauthorVaisman Chasin, Adrian
dc.contributor.imecauthorBury, Erik
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.orcidimecVaisman Chasin, Adrian::0000-0002-9940-0260
dc.contributor.orcidimecBury, Erik::0000-0002-5847-3949
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.date.accessioned2021-10-24T15:26:49Z
dc.date.available2021-10-24T15:26:49Z
dc.date.embargo9999-12-31
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29617
dc.identifier.urlhttp://ieeexplore.ieee.org/document/8268343/
dc.source.beginpage159
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate2/12/2017
dc.source.conferencelocationSan Francisco USA
dc.source.endpage162
dc.title

Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects

dc.typeProceedings paper
dspace.entity.typePublication
Files

Original bundle

Name:
36672.pdf
Size:
807.47 KB
Format:
Adobe Portable Document Format
Download
Publication available in collections:
Conference contributions