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Selective etching of SiGe for removal of dummy layers in fully silicided gate artchitectures

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dc.contributor.authorSnow, Jim
dc.contributor.authorVos, Rita
dc.contributor.authorKottantharayil, Anil
dc.contributor.authorKraus, Harald
dc.contributor.authorXu, Kaidong
dc.contributor.authorGrinninger, F.
dc.contributor.authorWagner, G.
dc.contributor.authorKovacs, F.
dc.contributor.authorMertens, Paul
dc.contributor.imecauthorVos, Rita
dc.contributor.imecauthorMertens, Paul
dc.date.accessioned2021-10-16T05:18:34Z
dc.date.available2021-10-16T05:18:34Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11250
dc.source.beginpage207
dc.source.conferenceCleaning Technology in Semiconductor Device Manufacturing IX
dc.source.conferencedate17/10/2005
dc.source.conferencelocationLos Angeles, CA USA
dc.source.endpage213
dc.title

Selective etching of SiGe for removal of dummy layers in fully silicided gate artchitectures

dc.typeProceedings paper
dspace.entity.typePublication
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