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FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic

Date

2002
Proceedings Paper
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dc.contributor.authorVlaminck, R.
dc.contributor.authorPletinckx, J.
dc.contributor.authorVerschuere, Stefaan
dc.contributor.authorBertrem, S.
dc.contributor.authorVandewege, Jan
dc.contributor.authorBoets, P.
dc.contributor.authorVanuytsel, G.
dc.contributor.authorTemmerman, S.
dc.date.accessioned2021-10-14T23:57:12Z
dc.date.available2021-10-14T23:57:12Z
dc.date.embargo9999-12-31
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7036
dc.source.beginpage716
dc.source.conferenceProceedings (on cd-rom) of the 6th WSEAS CSCC Multiconference - CSCC
dc.source.conferencedate7/07/2002
dc.source.conferencelocationRethymnon Greece
dc.title

FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic

dc.typeProceedings paper
dspace.entity.typePublication
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