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Sub-50nm gate patterning using line-trimming with 248nm or 193nm litho

Date

2002
Journal article
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dc.contributor.authorPollentier, Ivan
dc.contributor.authorJaenen, Patrick
dc.contributor.authorBaerts, Christina
dc.contributor.authorRonse, Kurt
dc.contributor.imecauthorPollentier, Ivan
dc.contributor.imecauthorJaenen, Patrick
dc.contributor.imecauthorBaerts, Christina
dc.contributor.imecauthorRonse, Kurt
dc.contributor.orcidimecPollentier, Ivan::0000-0002-4266-6500
dc.contributor.orcidimecRonse, Kurt::0000-0003-0803-4267
dc.date.accessioned2021-10-14T22:50:20Z
dc.date.available2021-10-14T22:50:20Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6733
dc.source.beginpage4
dc.source.endpage8
dc.source.issue2
dc.source.journalMicrolithography World
dc.source.volume11
dc.title

Sub-50nm gate patterning using line-trimming with 248nm or 193nm litho

dc.typeJournal article
dspace.entity.typePublication
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