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Investigation of performance improvement and gate-to-junction leakage reduction fot the 90nm CMOS gate stack architecture

Date

2002
Proceedings Paper
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dc.contributor.authorHenson, Kirklen
dc.contributor.authorKubicek, Stefan
dc.contributor.authorRedolfi, Augusto
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorJurczak, Gosia
dc.contributor.authorAugendre, Emmanuel
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.imecauthorJurczak, Gosia
dc.date.accessioned2021-10-14T21:46:05Z
dc.date.available2021-10-14T21:46:05Z
dc.date.embargo9999-12-31
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6382
dc.source.beginpage563
dc.source.conferenceESSDERC - 32nd European Solid-State Device Research Conference
dc.source.conferencedate24/09/2002
dc.source.conferencelocationFirenze Italy
dc.source.endpage566
dc.title

Investigation of performance improvement and gate-to-junction leakage reduction fot the 90nm CMOS gate stack architecture

dc.typeProceedings paper
dspace.entity.typePublication
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