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Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS

Date

2017
Proceedings Paper
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dc.contributor.authorFranco, Jacopo
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorVandooren, Anne
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorSioncke, Sonja
dc.contributor.authorPutcha, Vamsi
dc.contributor.authorVais, Abhitosh
dc.contributor.authorXie, Qi
dc.contributor.authorGivens, Michael
dc.contributor.authorTang, Fu
dc.contributor.authorJiang, X.
dc.contributor.authorSubirats, Alexandre
dc.contributor.authorVaisman Chasin, Adrian
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorKaczer, Ben
dc.contributor.authorLinten, Dimitri
dc.contributor.authorCollaert, Nadine
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorPutcha, Vamsi
dc.contributor.imecauthorVais, Abhitosh
dc.contributor.imecauthorXie, Qi
dc.contributor.imecauthorGivens, Michael
dc.contributor.imecauthorVaisman Chasin, Adrian
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecPutcha, Vamsi::0000-0003-1907-5486
dc.contributor.orcidimecVais, Abhitosh::0000-0002-0317-7720
dc.contributor.orcidimecVaisman Chasin, Adrian::0000-0002-9940-0260
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-24T04:48:57Z
dc.date.available2021-10-24T04:48:57Z
dc.date.embargo9999-12-31
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28350
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7936259
dc.source.beginpage2B-3.1
dc.source.conferenceIEEE International Reliability Physics Symposium - IRPS
dc.source.conferencedate2/04/2017
dc.source.conferencelocationMonterey, CA USA
dc.source.endpage2B3.5
dc.title

Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS

dc.typeProceedings paper
dspace.entity.typePublication
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