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DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance

 
dc.contributor.authorGaddemane, Gautam
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorBhuwalka, Krishna
dc.contributor.authorRzepa, Gerhard
dc.contributor.authorMirabelli, Gioele
dc.contributor.authorMatagne, Philippe
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorWu, Hao
dc.contributor.authorHellings, Geert
dc.contributor.authorLiu, Changze
dc.contributor.imecauthorGaddemane, Gautam
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorMirabelli, Gioele
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorHellings, Geert
dc.contributor.orcidimecGaddemane, Gautam::0000-0003-0067-8674
dc.contributor.orcidimecSchuddinck, Pieter::0000-0003-1893-3135
dc.contributor.orcidimecMirabelli, Gioele::0000-0001-7060-4836
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecMatagne, Philippe::0000-0003-0365-2066
dc.date.accessioned2025-05-13T12:06:41Z
dc.date.available2024-09-14T17:21:07Z
dc.date.available2025-05-13T12:06:41Z
dc.date.issued2024
dc.identifier.doi10.1109/EDTM58488.2024.10511609
dc.identifier.eisbn979-8-3503-7152-9
dc.identifier.isbn979-8-3503-8308-9
dc.identifier.issnN/A
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44483
dc.publisherIEEE
dc.source.beginpage226
dc.source.conference8th Electron Devices Technology & Manufacturing Conference (EDTM)
dc.source.conferencedateMAR 03-06, 2024
dc.source.conferencelocationBangalore
dc.source.endpage228
dc.source.journalN/A
dc.source.numberofpages3
dc.title

DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance

dc.typeProceedings paper
dspace.entity.typePublication
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