2026 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, ISSCC
Abstract
We present a 2048× time-interleaved slope-ADC implementing 7b, 175GS/s conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates static nonlinearities of the hierarchical sampling network. With only 0.063mm2 in 5nm CMOS, it is the smallest ultra-high-speed ADC reported to date with an excellent energy per sample of less than 2.16pJ.
