A finite element study of process induced stress in the transistor channel: effects of silicide contact and gate stack

dc.contributor.author	Torregiani, Cristina
dc.contributor.author	Liu, Joy
dc.contributor.author	Vandevelde, Bart
dc.contributor.author	Degryse, Dominiek
dc.contributor.author	Van Dal, Mark
dc.contributor.author	Benedetti, Alessandro
dc.contributor.author	Lauwers, Anne
dc.contributor.author	Maex, Karen
dc.contributor.imecauthor	Vandevelde, Bart
dc.contributor.imecauthor	Van Dal, Mark
dc.contributor.imecauthor	Lauwers, Anne
dc.contributor.imecauthor	Maex, Karen
dc.contributor.orcidimec	Vandevelde, Bart::0000-0002-6753-6438
dc.date.accessioned	2021-10-15T16:42:09Z
dc.date.available	2021-10-15T16:42:09Z
dc.date.issued	2004
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/9688
dc.source.beginpage	61
dc.source.conference	EuroSimE: 5th Int. Conf. on Thermal & Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems
dc.source.conferencedate	9/05/2004
dc.source.conferencelocation	Brussels Belgium
dc.source.endpage	68
dc.title	A finite element study of process induced stress in the transistor channel: effects of silicide contact and gate stack
dc.type	Proceedings paper
dspace.entity.type	Publication
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