Bias Temperature Instability in CMOS Digital Circuits from Planar to FinFET Nodes

dc.contributor.author	Kukner, Halil
dc.contributor.thesisadvisor	Lauwereins, Rudy
dc.contributor.thesisadvisor	Van der Perre, Liesbet
dc.date.accessioned	2021-10-22T20:16:03Z
dc.date.available	2021-10-22T20:16:03Z
dc.date.embargo	9999-12-31
dc.date.issued	2015-04
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/25498
dc.identifier.url	https://limo.libis.be/primo-explore/fulldisplay?docid=LIRIAS1734373&context=L&vid=Lirias&search_scope=Lirias&tab=default_tab&lang=en_US&fromSitemap=1
dc.title	Bias Temperature Instability in CMOS Digital Circuits from Planar to FinFET Nodes
dc.type	PHD thesis
dspace.entity.type	Publication
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