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Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs
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Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs
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Date
2005-10
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Wang, Hua
;
Miranda, Miguel
;
Papanikolaou, Antonis
;
Catthoor, Francky
;
Dehaene, Wim
Journal
IEEE Trans. VLSI Systems
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1908
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Acq. date: 2025-12-12
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Metrics
Views
1908
since deposited on 2021-10-16
1
last month
Acq. date: 2025-12-12
Citations