Temperature influence on analog parameters of vertical nanowire transistors

Abstract

This study investigates the impact of high temperatures on DC analog parameters of vertical nanowire pMOSFET (V-pFET). Measurements were performed at three temperatures (25 °C, 100 °C and 150 °C), where the main electrical parameters were analyzed. The results indicated an unexpected increase in the drain current and transconductance (gm) over the entire gate voltage range as temperature increased. This behavior is attributed to the competition of different effects such as the strong threshold voltage reduction and mobility degradation caused by the vertical electric field and the influence of high access resistance, which modifies the potential drop across the channel and alters the electric field distribution. On the other hand, the subthreshold slope (SS) exhibited the expected temperature dependence. However, when the temperature increases, the output conductance showed a slight variation. The Early voltage (VEA) increased with temperature, indicating a reduction in the Early effect. Despite this variation, the intrinsic voltage gain remained remarkably stable when expressed in decibels—approximately 34–36 dB for the device with 400 nanowires—demonstrating good thermal robustness of analog performance.