Publication:

Aging-Aware Timing Models for Reliability Enhancement of Inverter-Transmission Gate-Based Circuits

Date

2026
Journal article
https://doi.org/10.1109/mdat.2026.3677138
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0003-1188-4924
cris.virtualsource.department89856542-80db-428c-8ba5-3be494ea8b67
cris.virtualsource.orcid89856542-80db-428c-8ba5-3be494ea8b67
dc.contributor.authorGupta, Neha
dc.contributor.authorAcharya, Lomash Chandra
dc.contributor.authorSingh, Khoirom Johnson
dc.contributor.authorDargupally, Mahipal
dc.contributor.authorMishra, Neeraj
dc.contributor.authorSharma, Arvind
dc.contributor.authorMondal, Ajoy
dc.contributor.authorRamakrishnan, Venkatraman
dc.contributor.authorDasgupta, Sudeb
dc.contributor.authorBulusu, Anand
dc.date.accessioned2026-09-14T11:52:49Z
dc.date.available2026-09-14T11:52:49Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractEditor’s notes: The article introduces a variation-aware timing model, emphasizing aging, for the INV-Tx structure. By reducing aging-induced degradation in a thermometer encoder, this method can eliminate the need for errordetection circuits in data converters, ensuring accurate digital encoding. —Hemangee K. Kapoor, IIT Guwahati, India
dc.identifier.doi10.1109/mdat.2026.3677138
dc.identifier.eissn2168-2364
dc.identifier.issn2168-2356
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60344
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage23
dc.source.endpage29
dc.source.issue3
dc.source.journalIEEE DESIGN & TEST
dc.source.numberofpages7
dc.source.volume43
dc.title

Aging-Aware Timing Models for Reliability Enhancement of Inverter-Transmission Gate-Based Circuits

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-03-27
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-07
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