Publication:

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

Date

2013
Proceedings Paper
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dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorMoroz, Victor
dc.contributor.authorEneman, Geert
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorDehan, Morin
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorJang, Doyoung
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorThean, Aaron
dc.contributor.authorVerkest, Diederik
dc.contributor.authorSteegen, An
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorJang, Doyoung
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-21T07:45:21Z
dc.date.available2021-10-21T07:45:21Z
dc.date.embargo9999-12-31
dc.date.issued2013
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/22375
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6576617&queryText%3DLayout-induced+stress+effects+in+14nm
dc.source.beginpageT114
dc.source.conferenceSymposium on VLSI Technology
dc.source.conferencedate11/06/2013
dc.source.conferencelocationKyoto Japan
dc.source.endpageT115
dc.title

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

dc.typeProceedings paper
dspace.entity.typePublication
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