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CFET channel stack fabrication by wafer-to-wafer bonding and BESOI donor dismounting

 
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cris.virtual.orcid0000-0002-1014-7861
cris.virtual.orcid0000-0002-0282-8528
cris.virtual.orcid0000-0003-2890-0388
cris.virtual.orcid0000-0003-3513-6058
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cris.virtualsource.orcid26837d92-9214-4009-8525-3f8f947bf71c
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dc.contributor.authorTchouflian, Pauline
dc.contributor.authorBarge, D.
dc.contributor.authorHartmann, J.M.
dc.contributor.authorKerdilès, S.
dc.contributor.authorVincent, Larrey
dc.contributor.authorFournel, Frank
dc.contributor.authorLoup, V.
dc.contributor.authorHauchecorne, P.
dc.contributor.authorPapon. A.M.
dc.contributor.authorThouvard, A.
dc.contributor.authorRichy, J.
dc.contributor.authorMazel, Y.
dc.contributor.authorGauthier, N.
dc.contributor.authorFraczkiewicz, A.
dc.contributor.authorPares, G.
dc.contributor.authorSchippers, David
dc.contributor.authorJain, Utkarsh
dc.contributor.authorBrems, Steven
dc.contributor.authorLoo, Roger
dc.contributor.authorChan, BT
dc.contributor.orcidext0000-0003-3513-6058
dc.date.accessioned2026-08-25T07:21:47Z
dc.date.available2026-08-25T07:21:47Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractWe focus on the fabrication of a Complementary Field Effect Transistor (CFET) stack with two distinct four-periods Si/SiGe epitaxial superlattices isolated from one another by a thin thermal SiO2 layer. The structure is built using oxide-oxide wafer-to-wafer direct bonding and a Bond and Etch Back SOI (BESOI) approach to transfer the donor stack onto the receiver wafer. Key process steps of this fabrication flow are described including the superlattice epitaxial growth, the formation of the thermal oxide bonding layer, the molecular hydrophilic bonding and finally the donor wafer dismounting with extensive physical characterizations performed at each step. This process flow yields defect-free CFET channel stacks provided that the thermal oxide growth is well controlled and limited to a thickness of about 15 nm on top of each superlattice (i.e. a MDI thickness of at most 30 nm), a value compatible with the specifications of future CFET devices.
dc.description.wosFundingTextThis work was carried out in the frame of the NanoIC pilot line, which is supported by the Flemish government (Belgium) and received funding from the Chips Joint Undertaking through the Horizon Europe program under grant agreement No 101183277." Part of this work, carried out on the Platform for Nanocharacterisation (PFNC), was supported by the "Recherche Technologique de Base" and "France 2030"- ANR-22-PEEL-0014 '' programs of the French National Research Agency (ANR). As set out in the Grant Agreement, beneficiaries must ensure that at the latest at the time of publication, open access is provided via a trusted repository to the published version or the final peer-reviewed manuscript accepted for publication under the latest available version of the Creative Commons Attribution International Public Licence (CC BY). For the purpose of open access the authors have applied for a CC BY public copyright licence to any Author Accepted Manuscript version arising from this submission page.
dc.identifier.doi10.1016/j.mssp.2026.110826
dc.identifier.eissn1873-4081
dc.identifier.issn1873-4081
dc.identifier.issn1369-8001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60100
dc.identifier.urlhttps://www.sciencedirect.com/science/article/pii/S1369800126004221
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherELSEVIER SCI LTD
dc.rights.oaversionhttps://www.sciencedirect.com/science/article/pii/S1369800126004221
dc.source.beginpage110826
dc.source.journalMATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING
dc.source.numberofpages12
dc.source.volume214
dc.subject.keywordsGROWTH
dc.subject.keywordsGE
dc.title

CFET channel stack fabrication by wafer-to-wafer bonding and BESOI donor dismounting

dc.typeJournal article
dspace.entity.typePublication
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-07-14
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