Publication:

A model for MOS gate stack quality evaluation based on the gate current 1/f noise

Date

2008
Proceedings Paper
Simple item page Full metadata Statistics
 
dc.contributor.authorMagnone, P.
dc.contributor.authorCrupi, F.
dc.contributor.authorIannacone, G.
dc.contributor.authorGiusi, G.
dc.contributor.authorPace, C.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.accessioned2021-10-17T08:41:35Z
dc.date.available2021-10-17T08:41:35Z
dc.date.embargo9999-12-31
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14098
dc.source.beginpage141
dc.source.conference9th European Workshop on Ultimate Integration of Silicon - ULIS
dc.source.conferencedate12/03/2008
dc.source.conferencelocationUdine Italy
dc.source.endpage144
dc.title

A model for MOS gate stack quality evaluation based on the gate current 1/f noise

dc.typeProceedings paper
dspace.entity.typePublication
Files

Original bundle

Name:
17763.pdf
Size:
103.98 KB
Format:
Adobe Portable Document Format
Download
Publication available in collections:
Conference contributions