Optimization of 3D-DRAM Architecture With Oxide-Semiconductor Channel Through Process and Device Simulation

Abstract

Scaling of conventional 6F 2 1 T-1C DRAM is increasingly constrained as the buried-channel array transistor approaches its physical limits below the 10-nm node. Monolithic three-dimensional (3D) DRAM improves density through vertical stacking, while oxide semiconductor (OSC) channels promise low leakage. In this work we investigate a monolithically stackable OSC-based 3D-DRAM cell using an integrated framework combining process emulation, TCAD device simulation, parasitic extraction, and analytical modeling. Key geometric parameters are analyzed together with storage-node and parasitic capacitances extracted from process-emulated 3D structures. The optimized device achieves an on-current of 14.5 μ A/cell and a storage capacitance of 1.34 fF. The proposed architecture exhibits favorable intrinsic-cell retention, delay, and energy characteristics, while highlighting remaining challenges in process integration and reliability.