Publication:

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Date

2018
Proceedings Paper
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Author(s)

Sakhare, Sushil
;
Perumkunnil, Manu  
;
Huynh Bao, Trong
;
Rao, Siddharth  
;
Kim, Woojin  
;
Crotti, Davide  
;
Yasin, Farrukh  
;
Couet, Sebastien  
;
Swerts, Johan  
;
Kundu, Shreya  
;
Yakimets, Dmitry  
;
Baert, Rogier  
;
Oh, Hyungrock  
;
Spessot, Alessio  
;
Mocuta, Anda
;
Kar, Gouri Sankar  
;
Furnemont, Arnaud  

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