Publication:

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Date

2018
Proceedings Paper
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dc.contributor.authorSakhare, Sushil
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorRao, Siddharth
dc.contributor.authorKim, Woojin
dc.contributor.authorCrotti, Davide
dc.contributor.authorYasin, Farrukh
dc.contributor.authorCouet, Sebastien
dc.contributor.authorSwerts, Johan
dc.contributor.authorKundu, Shreya
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorBaert, Rogier
dc.contributor.authorOh, Hyungrock
dc.contributor.authorSpessot, Alessio
dc.contributor.authorMocuta, Anda
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorFurnemont, Arnaud
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorKim, Woojin
dc.contributor.imecauthorCrotti, Davide
dc.contributor.imecauthorYasin, Farrukh
dc.contributor.imecauthorCouet, Sebastien
dc.contributor.imecauthorSwerts, Johan
dc.contributor.imecauthorKundu, Shreya
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorOh, Hyungrock
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecYasin, Farrukh::0000-0002-7295-0254
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecOh, Hyungrock::0000-0001-5244-5755
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.date.accessioned2021-10-26T03:07:06Z
dc.date.available2021-10-26T03:07:06Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31710
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8614637
dc.source.beginpage420
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate1/12/2018
dc.source.conferencelocationSan Francisco USA
dc.source.endpage423
dc.title

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

dc.typeProceedings paper
dspace.entity.typePublication
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