Impact of gate stack layer composition on dynamic threshold voltage and analog parameters of Ge pMOSFETs

dc.contributor.author	Vinicius de Oliveira, Alberto
dc.contributor.author	Agopian, G.D.
dc.contributor.author	Martino, J.
dc.contributor.author	Simoen, Eddy
dc.contributor.author	Claeys, Cor
dc.contributor.author	Mertens, Hans
dc.contributor.author	Collaert, Nadine
dc.contributor.author	Thean, Aaron
dc.contributor.imecauthor	Simoen, Eddy
dc.contributor.imecauthor	Mertens, Hans
dc.contributor.imecauthor	Collaert, Nadine
dc.contributor.imecauthor	Thean, Aaron
dc.contributor.orcidimec	Simoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimec	Collaert, Nadine::0000-0002-8062-3165
dc.date.accessioned	2021-10-23T16:51:40Z
dc.date.available	2021-10-23T16:51:40Z
dc.date.issued	2016
dc.identifier.issn	1807-1953
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/27550
dc.source.beginpage	7
dc.source.endpage	12
dc.source.issue	1
dc.source.journal	Journal of Integrated Circuits and Systems
dc.source.volume	11
dc.title	Impact of gate stack layer composition on dynamic threshold voltage and analog parameters of Ge pMOSFETs
dc.type	Journal article
dspace.entity.type	Publication
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