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Articles
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
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A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
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Date
2004
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Resano Ezcaray, Jesús Javier
;
Verkest, Diederik
;
Mozos, Daniel
;
Vernalde, Serge
;
Catthoor, Francky
Journal
Microprocessors and microsystems
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2023
since deposited on 2021-10-15
Acq. date: 2025-12-16
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Views
2023
since deposited on 2021-10-15
Acq. date: 2025-12-16
Citations