Publication:

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Date

2004
Journal article
Simple item page Full metadata Statistics
 
dc.contributor.authorResano Ezcaray, Jesús Javier
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMozos, Daniel
dc.contributor.authorVernalde, Serge
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorVernalde, Serge
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-15T15:48:43Z
dc.date.available2021-10-15T15:48:43Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9506
dc.source.beginpage291
dc.source.endpage301
dc.source.issue5_6
dc.source.journalMicroprocessors and microsystems
dc.source.volume28
dc.title

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

dc.typeJournal article
dspace.entity.typePublication
Files
Publication available in collections:
Articles