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Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Date

2016-11
Journal article
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dc.contributor.authorKarageorgos, Ioannis
dc.contributor.authorRyckaert, Julien
dc.contributor.authorGronheid, Roel
dc.contributor.authorTung, Maryann C.
dc.contributor.authorWong, H.-S. Philip
dc.contributor.authorKarageorgos, Evangelos
dc.contributor.authorCroes, Kris
dc.contributor.authorBekaert, Joost
dc.contributor.authorVandenberghe, Geert
dc.contributor.authorStucchi, Michele
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorGronheid, Roel
dc.contributor.imecauthorBekaert, Joost
dc.contributor.imecauthorVandenberghe, Geert
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecBekaert, Joost::0000-0003-3075-3479
dc.date.accessioned2021-10-23T11:40:14Z
dc.date.available2021-10-23T11:40:14Z
dc.date.issued2016-11
dc.identifier.issn1932-5150
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26807
dc.identifier.urlhttp://dx.doi.org/10.1117/1.JMM.15.4.043506
dc.source.beginpage43506
dc.source.issue4
dc.source.journalJournal of Micro/Nanolithography MEMS and MOEMS
dc.source.volume15
dc.title

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

dc.typeJournal article
dspace.entity.typePublication
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