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Scaling induced drain current degradation for low voltage operation of CMOS technology below 100 nm: impact of non-scalable parameters

Date

2000
Proceedings Paper
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dc.contributor.authorHenson, Kirklen
dc.contributor.authorKubicek, Stefan
dc.contributor.authorDe Meyer, Kristin
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDe Meyer, Kristin
dc.date.accessioned2021-10-14T13:03:30Z
dc.date.available2021-10-14T13:03:30Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4424
dc.source.beginpage13
dc.source.conferenceProceedings ULIS Workshop; 20-21 January 2000; Grenoble, France.
dc.source.conferencelocation
dc.source.endpage17
dc.title

Scaling induced drain current degradation for low voltage operation of CMOS technology below 100 nm: impact of non-scalable parameters

dc.typeProceedings paper
dspace.entity.typePublication
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