Publication:
Achieving 1ppm write-error rate in SOT-MRAM with synthetic antiferromagnetic free layer
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| dc.contributor.author | Nguyen, Van Dai | |
| dc.contributor.author | Talmelli, Giacomo | |
| dc.contributor.author | Gama Monteiro Junior, Maxwel | |
| dc.contributor.author | Palomino, A. | |
| dc.contributor.author | Kateel, Vaishnavi | |
| dc.contributor.author | Giuliano, Domenico | |
| dc.contributor.author | Van Beek, Simon | |
| dc.contributor.author | Vander Meeren, N. | |
| dc.contributor.author | Franchina Vergel, Nathali | |
| dc.contributor.author | Wostyn, Kurt | |
| dc.contributor.author | Couet, Sebastien | |
| dc.date.accessioned | 2026-04-21T10:23:30Z | |
| dc.date.available | 2026-04-21T10:23:30Z | |
| dc.date.createdwos | 2026-03-18 | |
| dc.date.issued | 2024 | |
| dc.description.abstract | We demonstrate the functionality of a perpendicular spin-orbit torque (SOT)-MRAM with a synthetic anti ferromagnetic (SAF) free layer in the magnetic tunnel junction (MTJ) pillar. This novel stack design significantly reduces the write error rate (WER) to as low as 10‒6 while maintaining a thermal budget of 400°C, ensuring BEOL compatibility. Our micromagnetic simulations systematically guide the selection of key material parameters, ensuring reliable operation in real device demonstration. This correlation between simulation-guided material selection and experimental validation is crucial for advancing SOT-MRAM technology. Finally, our devices are fabricated on 300 mm wafers, enabling significant strides in technological integration. | |
| dc.description.wosFundingText | This work is supported by imec's industrial affiliation program on MRAM devices. We also acknowledge support from the ECSEL Joint Undertaking Program (grant No. 876925-project ANDANTE). The authors gratefully acknowledge the P-line for operational support. D. Giuliano gratefully acknowledges MO Flanders for a Strategic Basic Research PhD fellowship. | |
| dc.identifier.doi | 10.1109/iedm50854.2024.10873509 | |
| dc.identifier.issn | 2380-9248 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59146 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
| dc.source.conferencedate | 2024-12-07 | |
| dc.source.conferencelocation | San Francisco | |
| dc.source.journal | 2024 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | |
| dc.source.numberofpages | 4 | |
| dc.title | Achieving 1ppm write-error rate in SOT-MRAM with synthetic antiferromagnetic free layer | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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