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Design Considerations of High-speed Analog De-multiplexer

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-9672-6652
cris.virtual.orcid0000-0002-0212-6876
cris.virtualsource.department3dada851-d554-4718-8993-44b5bf752bf5
cris.virtualsource.departmentfaca5179-50c0-4594-9de5-2e2431aa68c0
cris.virtualsource.orcid3dada851-d554-4718-8993-44b5bf752bf5
cris.virtualsource.orcidfaca5179-50c0-4594-9de5-2e2431aa68c0
dc.contributor.authorNiu, Shengpu
dc.contributor.authorYin, Xin
dc.date.accessioned2026-03-16T15:16:21Z
dc.date.available2026-03-16T15:16:21Z
dc.date.createdwos2025-11-21
dc.date.issued2025
dc.description.abstractTo overcome the bandwidth and sampling rate limitations of the CMOS ADCs, a high-speed analog de-multiplexer (ADEMUX) offers scalability for the future heterogeneous ADC and the wireline receivers. We discuss the design considerations of high-speed ADEMUX, including architecture comparison, and circuit design.
dc.description.wosFundingTextThe work was partly supported by Ghent University GOA and EU POETICS under Grant 871769.
dc.identifier.doi10.1109/sum65312.2025.11121811
dc.identifier.isbn979-8-3315-0904-0
dc.identifier.issn1099-4742
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/58852
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE PHOTONICS SOCIETY SUMMER TOPICALS MEETING SERIES, SUM
dc.source.conferencedate2025-07-21
dc.source.conferencelocationBerlin
dc.source.journal2025 IEEE PHOTONICS SOCIETY SUMMER TOPICALS MEETING SERIES, SUM
dc.source.numberofpages2
dc.title

Design Considerations of High-speed Analog De-multiplexer

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-11-24
imec.internal.sourcecrawler
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