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Joint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193i

Date

2011
Proceedings Paper
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dc.contributor.authorDe Bisschop, Peter
dc.contributor.authorLaenens, Bart
dc.contributor.authorIwase, Kazuya
dc.contributor.authorYao, Teruyoshi
dc.contributor.authorDusa, Mircea
dc.contributor.authorSmayling, M.
dc.contributor.imecauthorDe Bisschop, Peter
dc.contributor.imecauthorDusa, Mircea
dc.date.accessioned2021-10-19T13:02:53Z
dc.date.available2021-10-19T13:02:53Z
dc.date.embargo9999-12-31
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18774
dc.source.beginpage79730B
dc.source.conferenceOptical Microlithography XXIV
dc.source.conferencedate27/02/2011
dc.source.conferencelocationSan Jose, CA USA
dc.title

Joint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193i

dc.typeProceedings paper
dspace.entity.typePublication
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