Publication:

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Date

2014-09

Proceedings Paper

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Author(s)

Huynh Bao, Trong

;

Yakimets, Dmitry

;

Ryckaert, Julien

;

;

;

Veloso, Anabela

;

Boemmels, Juergen

;

Collaert, Nadine

;

Roussel, Philippe

;

Demuynck, Steven

;

Raghavan, Praveen

;

Mercha, Abdelkarim

;

;

Verkest, Diederik

;

;

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1938 since deposited on 2021-10-22

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Acq. date: 2026-02-24