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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Date

2014-09
Proceedings Paper
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dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorRyckaert, Julien
dc.contributor.authorCiofi, Ivan
dc.contributor.authorBaert, Rogier
dc.contributor.authorVeloso, Anabela
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorCollaert, Nadine
dc.contributor.authorRoussel, Philippe
dc.contributor.authorDemuynck, Steven
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorTokei, Zsolt
dc.contributor.authorVerkest, Diederik
dc.contributor.authorThean, Aaron
dc.contributor.authorWambacq, Piet
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorCiofi, Ivan
dc.contributor.imecauthorBaert, Rogier
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorBoemmels, Juergen
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecCiofi, Ivan::0000-0003-1374-4116
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.date.accessioned2021-10-22T02:11:22Z
dc.date.available2021-10-22T02:11:22Z
dc.date.issued2014-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23977
dc.identifier.urlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6948768
dc.source.beginpage102
dc.source.conference44th European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate22/09/2014
dc.source.conferencelocationVenice Italy
dc.source.endpage105
dc.title

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

dc.typeProceedings paper
dspace.entity.typePublication
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