A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

dc.contributor.author	Araga, Yuuki
dc.contributor.author	Miura, Ranto
dc.contributor.author	Nagata, Makoto
dc.contributor.author	Roda Neve, Cesar
dc.contributor.author	De Vos, Joeri
dc.contributor.author	Van der Plas, Geert
dc.contributor.author	Beyne, Eric
dc.contributor.imecauthor	De Vos, Joeri
dc.contributor.imecauthor	Van der Plas, Geert
dc.contributor.imecauthor	Beyne, Eric
dc.contributor.orcidimec	De Vos, Joeri::0000-0002-9332-9336
dc.contributor.orcidimec	Van der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimec	Beyne, Eric::0000-0002-3096-050X
dc.date.accessioned	2021-10-22T00:43:47Z
dc.date.available	2021-10-22T00:43:47Z
dc.date.issued	2014
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/23496
dc.source.beginpage	1
dc.source.conference	Electronics System-Integration Technology Conference - ESTC
dc.source.conferencedate	16/09/2014
dc.source.conferencelocation	Helsinki Finland
dc.source.endpage	5
dc.title	A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
dc.type	Proceedings paper
dspace.entity.type	Publication
Files
Publication available in collections:	Conference contributions

Date