Publication:

Wafer-to-Wafer Bonding with Saddle-shaped Wafers

 
dc.contributor.authorKang, Shuo
dc.contributor.authorIacovo, Serena
dc.contributor.authorD'have, Koen
dc.contributor.authorOkudur, Oguzhan Orkut
dc.contributor.authorAlexeev, Anton
dc.contributor.authorPlach, Thomas
dc.contributor.authorProbst, Gernot
dc.contributor.authorDing, Taotao
dc.contributor.authorWimplinger, Markus
dc.contributor.authorUhrmann, Thomas
dc.contributor.authorDe Vos, Joeri
dc.contributor.authorBeyer, Gerald
dc.contributor.authorBeyne, Eric
dc.date.accessioned2026-03-24T13:51:41Z
dc.date.available2026-03-24T13:51:41Z
dc.date.createdwos2025-10-31
dc.date.issued2025
dc.description.abstractWafer bonding is becoming a key enabling technology for advanced semiconductor devices, and as pitch scaling continues, precise wafer-to-wafer alignment becomes increasingly critical. Variations in incoming wafer shape can significantly impact bonding overlay. In this study, we investigate the bonding of wafers with saddle shape, a deformation commonly observed in 3D NAND wafers. Our findings show that bonding errors are much higher for these wafers compared to those with more symmetric shapes, with a significant portion of the overlay attributed to asymmetric scaling. Enhancing asymmetric scaling compensation is crucial for reducing bonding overlay, benefiting not only 3D NAND-to-logic bonding but also other applications involving wafers with minor shape asymmetries. A method for reducing asymmetry utilizing the top chuck control is presented, along with a discussion of its limitations. Additionally, we discuss the measurement results of backside post-thinning lithography overlay with higher order correction, which is crucial for applications requiring highly accurate backside patterning alignment.
dc.identifier.doi10.1109/ECTC51687.2025.00347
dc.identifier.isbn979-8-3315-3933-7
dc.identifier.issn0569-5503
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/58933
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE COMPUTER SOC
dc.source.beginpage2001
dc.source.conferenceIEEE 75th Electronic Components and Technology Conference (ECTC)
dc.source.conferencedate2025-03-27
dc.source.conferencelocationDallas
dc.source.journal2025 IEEE 75TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC
dc.source.numberofpages6
dc.title

Wafer-to-Wafer Bonding with Saddle-shaped Wafers

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
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