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Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond
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Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond
Date
2017-05
Journal article
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31739.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Huynh Bao, Trong
;
Ryckaert, Julien
;
Tokei, Zsolt
;
Mercha, Abdelkarim
;
Verkest, Diederik
;
Thean, Aaron
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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1956
since deposited on 2021-10-24
Acq. date: 2025-12-08
Citations
Metrics
Views
1956
since deposited on 2021-10-24
Acq. date: 2025-12-08
Citations