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Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond

Date

2017-05
Journal article
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dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorRyckaert, Julien
dc.contributor.authorTokei, Zsolt
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorVerkest, Diederik
dc.contributor.authorThean, Aaron
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.thesisadvisorWambacq, Piet
dc.date.accessioned2021-10-24T06:02:59Z
dc.date.available2021-10-24T06:02:59Z
dc.date.embargo9999-12-31
dc.date.issued2017-05
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28555
dc.identifier.urlhttps://doi.org/10.1109/TVLSI.2017.2647853
dc.source.beginpage1669
dc.source.endpage1680
dc.source.issue5
dc.source.journalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.source.volume25
dc.title

Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond

dc.typeJournal article
dspace.entity.typePublication
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