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Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass
Publication:
Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass
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Date
2018
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Pirotte, Niels
;
Vliegen, Jo
;
Batina, Lej
;
Mentens, Nele
Journal
Abstract
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1859
since deposited on 2021-10-26
Acq. date: 2025-12-11
Citations
Metrics
Views
1859
since deposited on 2021-10-26
Acq. date: 2025-12-11
Citations