Publication:

Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass

Date

2018
Proceedings Paper
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dc.contributor.authorPirotte, Niels
dc.contributor.authorVliegen, Jo
dc.contributor.authorBatina, Lej
dc.contributor.authorMentens, Nele
dc.contributor.imecauthorMentens, Nele
dc.date.accessioned2021-10-26T01:15:53Z
dc.date.available2021-10-26T01:15:53Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31534
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8491866
dc.source.beginpage1
dc.source.conference2018 21st Euromicro Conference on Digital System Design (DSD)
dc.source.conferencedate29/08/2018
dc.source.conferencelocationPrague Czech Republic
dc.source.endpage8
dc.title

Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass

dc.typeProceedings paper
dspace.entity.typePublication
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