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Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Date

2016
Proceedings Paper
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dc.contributor.authorKarageorgos, Ioannis
dc.contributor.authorRyckaert, Julien
dc.contributor.authorTung, C. Maryann
dc.contributor.authorWong, H.-S. Philip
dc.contributor.authorGronheid, Roel
dc.contributor.authorBekaert, Joost
dc.contributor.authorCroes, Kris
dc.contributor.authorKarageorgos, Evangelos
dc.contributor.authorVandenberghe, Geert
dc.contributor.authorStucchi, Michele
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorGronheid, Roel
dc.contributor.imecauthorBekaert, Joost
dc.contributor.imecauthorVandenberghe, Geert
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecBekaert, Joost::0000-0003-3075-3479
dc.date.accessioned2021-10-23T11:40:34Z
dc.date.available2021-10-23T11:40:34Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26808
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2505330
dc.source.beginpage97810N
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability X
dc.source.conferencedate21/02/2016
dc.source.conferencelocationSan Jose, CA USA
dc.title

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

dc.typeProceedings paper
dspace.entity.typePublication
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