Publication:

Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO2/HfO2 Gate Dielectrics

Date

2023
Journal article
https://doi.org/10.1109/TNS.2023.3239844
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dc.contributor.authorLi, Kan
dc.contributor.authorLuo, Xuyi
dc.contributor.authorRony, M. W.
dc.contributor.authorGorchichko, Mariia
dc.contributor.authorHiblot, Gaspard
dc.contributor.authorVan Huylenbroeck, Stefaan
dc.contributor.authorJourdain, Anne
dc.contributor.authorAlles, Michael L.
dc.contributor.authorReed, Robert A.
dc.contributor.authorZhang, En Xia
dc.contributor.authorFleetwood, Daniel M.
dc.contributor.authorSchrimpf, Ronald D.
dc.contributor.imecauthorHiblot, Gaspard
dc.contributor.imecauthorVan Huylenbroeck, Stefaan
dc.contributor.imecauthorJourdain, Anne
dc.contributor.orcidimecHiblot, Gaspard::0000-0002-3869-965X
dc.contributor.orcidimecVan Huylenbroeck, Stefaan::0000-0001-9978-3575
dc.contributor.orcidimecJourdain, Anne::0000-0002-7610-0513
dc.date.accessioned2023-07-04T13:14:22Z
dc.date.available2023-05-27T20:01:00Z
dc.date.available2023-07-04T13:14:22Z
dc.date.embargo9999-12-31
dc.date.issued2023
dc.description.wosFundingTextThis work was supported in part by the Department of the Defense Threat Reduction Agency through its Basic Research Program and in part by the Air Force Office of Scientific Research under Grant FA9550-17-1-0046 and Grant FA9550-22-1-0012.
dc.identifier.doi10.1109/TNS.2023.3239844
dc.identifier.issn0018-9499
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41653
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage442
dc.source.endpage448
dc.source.issue4
dc.source.journalIEEE TRANSACTIONS ON NUCLEAR SCIENCE
dc.source.numberofpages7
dc.source.volume70
dc.subject.keywords1/F NOISE
dc.subject.keywordsBIAS DEPENDENCE
dc.subject.keywordsUNIFIED MODEL
dc.subject.keywordsOXIDE-TRAP
dc.subject.keywordsMOS
dc.subject.keywordsTEMPERATURE
dc.subject.keywordsDEFECTS
dc.subject.keywordsDEVICES
dc.title

Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO2/HfO2 Gate Dielectrics

dc.typeJournal article
dspace.entity.typePublication
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