Publication:

Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

Date

2010
Journal article
Simple item page Full metadata Statistics
 
dc.contributor.authorYang, Yu
dc.contributor.authorLabie, Riet
dc.contributor.authorLing, Fangzhou
dc.contributor.authorZhao, Chao
dc.contributor.authorRadisic, Alex
dc.contributor.authorVan Olmen, Jan
dc.contributor.authorTravaly, Youssef
dc.contributor.authorVerlinden, Bert
dc.contributor.authorDe Wolf, Ingrid
dc.contributor.imecauthorLabie, Riet
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorVan Olmen, Jan
dc.contributor.imecauthorDe Wolf, Ingrid
dc.contributor.orcidimecLabie, Riet::0000-0002-1401-1291
dc.contributor.orcidimecDe Wolf, Ingrid::0000-0003-3822-5953
dc.date.accessioned2021-10-19T00:41:47Z
dc.date.available2021-10-19T00:41:47Z
dc.date.issued2010
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18381
dc.identifier.urlhttp://dx.doi.org/10.1016/j.microrel.2010.07.019
dc.source.beginpage1636
dc.source.endpage1640
dc.source.issue9_11
dc.source.journalMicroelectronics Reliability
dc.source.volume50
dc.title

Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

dc.typeJournal article
dspace.entity.typePublication
Files
Publication available in collections:
Articles