Publication:

Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures

Date

2021
Journal article
https://doi.org/10.1109/TED.2021.3077349
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dc.contributor.authorSilva, Vanessa C. P.
dc.contributor.authorPerina, Welder F.
dc.contributor.authorMartino, Joao A.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorVeloso, Anabela
dc.contributor.authorAgopian, Paula G. D.
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.orcidextPerina, Welder F.::0000-0001-6205-351X
dc.contributor.orcidextMartino, Joao A.::0000-0001-8121-6513
dc.contributor.orcidextAgopian, Paula G. D.::0000-0002-0886-7798
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.accessioned2022-03-07T10:17:33Z
dc.date.available2022-03-07T10:17:33Z
dc.date.issued2021
dc.identifier.doi10.1109/TED.2021.3077349
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39329
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage3630
dc.source.endpage3635
dc.source.issue7
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages6
dc.source.volume68
dc.subject.keywordsLOW-FREQUENCY NOISE
dc.subject.keywordsVOLTAGE
dc.subject.keywordsSOI
dc.title

Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures

dc.typeJournal article
dspace.entity.typePublication
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