Publication:

Device process and architecture aware physical TCAD model for ultra-thin film a-IGZO transistors

Date

2025
Proceedings Paper
https://doi.org/10.1109/sispad66650.2025.11186376
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0003-0557-5260
cris.virtual.orcid0000-0002-3947-1948
cris.virtual.orcid0009-0003-9520-9631
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0001-9489-3396
cris.virtual.orcid0000-0002-1960-5136
cris.virtual.orcid0000-0002-5849-3384
cris.virtualsource.departmentc49fd1e2-a117-4839-80dc-0e884525b195
cris.virtualsource.departmentfbb111b9-7a59-4ef8-ad0b-4868e652f5e8
cris.virtualsource.departmentd93563e6-7827-4306-880c-b983e6f3762a
cris.virtualsource.department51733ec3-79c7-4c34-9f77-3a0563c8f5a1
cris.virtualsource.departmente4a94a6f-d25b-48db-abde-900f33e73904
cris.virtualsource.department169042dc-ef52-4e63-84b3-d182f6171fa2
cris.virtualsource.departmenta939d7ba-3233-4873-8fde-6410209de08a
cris.virtualsource.department8311c522-c607-40bc-8b22-a02dd2896062
cris.virtualsource.departmentdb73cf2d-2000-429c-bc92-553a1ef3e876
cris.virtualsource.orcidc49fd1e2-a117-4839-80dc-0e884525b195
cris.virtualsource.orcidfbb111b9-7a59-4ef8-ad0b-4868e652f5e8
cris.virtualsource.orcidd93563e6-7827-4306-880c-b983e6f3762a
cris.virtualsource.orcid51733ec3-79c7-4c34-9f77-3a0563c8f5a1
cris.virtualsource.orcide4a94a6f-d25b-48db-abde-900f33e73904
cris.virtualsource.orcid169042dc-ef52-4e63-84b3-d182f6171fa2
cris.virtualsource.orcida939d7ba-3233-4873-8fde-6410209de08a
cris.virtualsource.orcid8311c522-c607-40bc-8b22-a02dd2896062
cris.virtualsource.orciddb73cf2d-2000-429c-bc92-553a1ef3e876
dc.contributor.authorSubhechha, Subhali
dc.contributor.authorTang, Hongwei
dc.contributor.authorArutchelvan, Goutham
dc.contributor.authorEneman, Geert
dc.contributor.authorYengula Venkata Ramana, Bhuvaneshwari
dc.contributor.authorvan Setten, Michiel
dc.contributor.authorWan, Yiqun
dc.contributor.authorRassoul, Nouredine
dc.contributor.authorBelmonte, Attilio
dc.contributor.authorKar, Gouri Sankar
dc.date.accessioned2026-09-14T11:06:03Z
dc.date.available2026-09-14T11:06:03Z
dc.date.createdwos2026
dc.date.issued2025
dc.description.abstractPerformance of amorphous IGZO thin film transistors is strongly linked to their device architecture and processing. We identify the critical parameters determining device performance across bias ranges through experiments and TCAD simulations. Based on this, we present a process-aware TCAD model describing transfer characteristics of three device architectures. Insights from this modeling work are used to understand the impact of various process steps on the device operation and propose design guidelines for performance optimization.
dc.description.wosFundingTextThe authors would like to thank the support of imec's Industrial Partners in the Active Memory Program. This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu.
dc.identifier.doi10.1109/sispad66650.2025.11186376
dc.identifier.isbn979-8-3315-4884-1
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60336
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.beginpage1
dc.source.conferenceInternational Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
dc.source.conferencedate2025-09-24
dc.source.conferencelocationGrenoble
dc.source.endpage4
dc.source.journal2025 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, SISPAD
dc.source.numberofpages4
dc.title

Device process and architecture aware physical TCAD model for ultra-thin film a-IGZO transistors

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-13
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