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Impact of elevated source drain architecture on ESD protection devices for a 90 nm CMOS technology node

Date

2003-09
Proceedings Paper
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dc.contributor.authorThijs, Steven
dc.contributor.authorDe Heyn, Vincent
dc.contributor.authorVassilev, Vesselin
dc.contributor.authorMahadeva Iyer, Natarajan
dc.contributor.authorLinten, Dimitri
dc.contributor.authorJeamsaksiri, Wutthinan
dc.contributor.authorDaenen, T.
dc.contributor.authorJurczak, Gosia
dc.contributor.authorRooyackers, Rita
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorDe Heyn, Vincent
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.date.accessioned2021-10-15T06:57:09Z
dc.date.available2021-10-15T06:57:09Z
dc.date.issued2003-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8209
dc.source.beginpage242
dc.source.conferenceEOS/ESD Symposium
dc.source.conferencedate21/09/2003
dc.source.conferencelocationLas Vegas, NV USA
dc.source.endpage249
dc.title

Impact of elevated source drain architecture on ESD protection devices for a 90 nm CMOS technology node

dc.typeProceedings paper
dspace.entity.typePublication
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