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CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
Publication:
CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
Date
2024
Proceedings Paper
https://doi.org/10.1109/VLSITSA60681.2024.10546439
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Horiguchi, Naoto
;
Mertens, Hans
;
Ritzenthaler, Romain
;
Subramanian, Sujith
;
Weckx, Pieter
;
Schuddinck, Pieter
;
Veloso, Anabela
;
Yang, Sheng
;
Serbulova, Kateryna
;
Ryckaert, Julien
Journal
N/A
Abstract
Description
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516
since deposited on 2024-08-16
470
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Acq. date: 2025-10-24
Citations
Metrics
Views
516
since deposited on 2024-08-16
470
item.page.metrics.field.last-week
Acq. date: 2025-10-24
Citations